The present invention relates to transition logic circuits for use in the interface between logic gate circuits from different logic families, and more particularly, to transition circuits for use at the interface between logic circuits of the transistor-transistor logic (TTL) circuit family and the complementary metal-oxide-semiconductor field-effect transistor (CMOS FET) logic circuit family.
Various kinds of logic gate circuit families each have their peculiar advantages and disadvantages. At interfaces between different systems or system components, one system or a component thereof will have used logic gate circuits from one kind of logic family while the subsequent system, or a component thereof, will have for one or another reason used gates from another kind of logic family. Also quite often in the integrated circuit technology of today, the optimum solution for the design of a particular logic system is to use logic gate circuits from more than one kind of logic family in accomplishing such a design in the form of a monolithic integrated circuit. These situations pose some difficulty because the logic gate circuits of each different logic family must be operated at differing voltage levels for each logic state and these levels, in each family, will have a different voltage value separating them. This situation requires some sort of transition circuit to permit the logic signals, obtained from logic gate circuits in one kinds of logic family, to be applied to logic gate circuits of another kind of logic family.
However, the design of such transition circuits must not seriously compromise a performance of an entire logic system involving gates taken from various kinds of logic families. Therefore, the transition circuit must operate with approximately the same switching rapidity as do the logic gate circuits in each of the logic gate family types being interfaced. So, where two different kinds of logic families are intended to be used in a system and a logic gate from one must be at an interface with another, and each are capable of very rapid switching, the transition circuit at the interface between the two gates must also be capable of very rapid switching. Yet, at the same time, this transition circuit must provide the transition between the various voltage levels normally employed in each of the two logic family types.
Further, the transition circuit must be capatible with the fabrication process for forming at least one kind of the chosen logic gate families in order that the transition circuit may be integrated on the same monolithic integrated circuit chip as that part of the system of such logic gate family. Also, the space taken by the transition circuit being formed on the monolithic integrated circuit chips should be as small as possible to aid in achieving a high density of logic functions in such chips.
A commonly encountered situation is in going from the logic levels used with TTL logic circuits to those used with CMOS FET logic circuits. Assuming that the power supply voltage available is a positive 5.0 volts with respect to ground, the TTL logic family has a logic gate output voltage specified as being 0.4 volts as the maximum output voltage for logic level "0". The specified at output voltage value for a logic level "1" for this family is a minimum voltage value of 2.4 volts.
To maintain an adequate noise margin during operation, a circuit driven by such a TTL logic gate should accept as a "0" logic level of voltage somewhat greater than 0.4 volts, and should accept as a "1" logic level a voltage somewhat less than 2.4 volts. Best of all in this reagard, a circuit to follow such a TTL logic gate should be caused to switch between it logic levels in approximately the center of this range of TTL logic family output voltages, or somewhere around 1.4 volts to provide the greatest possible symmetric noise margins.
For the same positive 5 volt power supply with respect to ground, a CMOS FET logic circuit output will operate with a "0" logic level at a voltage much nearer ground than a TTL logic gate, and a "1" logic level much nearer the 5 volt supply level. More importantly, the input voltage switching point of a CMOS FET logic gate circuit is typically one half of the power supply voltage, or around 2.5 volts in this instance. Obviously, this is incompatible with the TTL logic gate output voltage midpoint of 1.4 volts occurring midway between the worst case logic level voltage values of 0.4 volts and 2.4 volts. Further compounding the situation is that the switching point for CMOS FET logic gate circuits--one-half the power supply voltage--is but a nominal switching point. The actual switching point can vary considerably as a result of variations in the fabrication process for the CMOS FET logic circuit, and also through power supply variations and temperature variations. Thus, a transition circuit is desired which provides a transition from the TTL logic family to the CMOS FET logic family in view of these differences, while at the same time meeting the above indicated goals.